Theora Hardware: Difference between revisions

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(rewrite based on output of Google SoC2006)
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Currently Theora decoding is not provided by any hardware.
The [http://www.xilinx.com/publications/xcellonline/xcell_53/xc_video53.htm Elphel 333] can encode a Theora stream.
The [http://www.xilinx.com/publications/xcellonline/xcell_53/xc_video53.htm Elphel 333] can encode a theora stream though.


Hardware decoders for Theora are just beginning to appear.  The Google "Summer Of Code 2006" produced an FPGA decoder implementation in Verilog.
* [http://svn.xiph.org/trunk/theora-fpga/ Verilog source]
* [http://www.students.ic.unicamp.br/~ra023772/projects.html Author's University projects page]


But, there is an accepted proposal to Google Summer Of Code 2006 that the goal is to do a Hardware Implementation of the Theora Decoding Algorithm.
Here are two presentations that the author of the SOC proposal presented in his University:
 
* [http://svn.xiph.org/trunk/theora-fpga/doc/hard_theora.pdf Theora Hardware Decoding]
The intent is to get a FPGA embeded system decoding Theora Streams in real-time.
* [http://svn.xiph.org/trunk/theora-fpga/doc/video_enc_basic.pdf Video Encoding: Basic Principles]
 
The complete text of the project proposed is here:
 
* [http://atlas.lsc.ic.unicamp.br/%7Eportavales/wp-content/uploads/2006/05/soc_proposal.txt SOC - Theora Hardware Decoding]
 
 
As soon as possible, there will be more specific information about the implementation, but to begin, there are two presentations that the author of the SOC proposal presented in his University:
 
* [http://atlas.lsc.ic.unicamp.br/%7Eportavales/wp-content/uploads/2006/05/hard_theora.pdf Theora Hardware Decoding]
* [http://atlas.lsc.ic.unicamp.br/%7Eportavales/wp-content/uploads/2006/05/video_enc_basic.pdf Video Encoding: Basic Principles]


== See also ==
== See also ==

Revision as of 20:18, 6 February 2007

The Elphel 333 can encode a Theora stream.

Hardware decoders for Theora are just beginning to appear. The Google "Summer Of Code 2006" produced an FPGA decoder implementation in Verilog.

Here are two presentations that the author of the SOC proposal presented in his University:

See also

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